Design, develop, and debug Fill components of Process Design Kits (PDKs)
Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.
Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions.
Automate workflows to enhance efficiency, accuracy, and deployment across design teams.
Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.
Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.
Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.
Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of relevant experience, Master's degree with 6+ years of relevant experience, OR PhD with 3+ years of relevant experience.
Proficiency in scripting languages such as Python, Tcl, or Perl for automation
Expertise in EDA tools, including Calibre, ICV, or Pegasus, with strong skills in developing and debugging rule decks (e.g., SVRF/TVF, PXL, PVL/PVTCL).
Solid understanding of semiconductor device physics, process technology, and design rules.
Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
Strong knowledge of Unix/Linux platforms and computing environments.

Senior Density Fill Development Engineer

Key skills