Senior Design Verification Engineer – Neuromorphic Computing

Role Overview

• Creating unit-level and system-level test plans.
• Write directed and random tests for design partitions and chip-level.
• Debugging test failures, tracking coverage and working with designers to fix failures and improve coverage.
• Maintaining assertions, scoreboards and any tools/flows that are developed.

Requirements

• Bachelors and 8+ years OR Masters and 6+ years of silicon engineering experience.
• 5+ years of verification experience in SoC accelerators or custom ASIC designs.
• 5+ years of experience in UVM/OVM and constrained random verification methods.
• 2+ years of experience owning the entire verification stack including test planning, test development, coverage tracking, and interfacing with emulation models.
• 1+ year of experience using AI tools for test generation, debugging and improving overall productivity.
• Experienced in neuromorphic computing or AI/ML accelerator design.
• Experience with commercial Verification IPs for standard IO interfaces, PHYs, and protocols such as Ethernet, PCIE, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204.
• Experience with DFX, low power and UPF verification techniques.
• Experience leading silicon design/verification teams.

Benefits

• health, retirement, and vacation