About this role

responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes
directly interface with key Intel foundry customers to understand technology and library gaps
drive co-optimization with Intel foundry technology development teams and EDA partners
optimizing library circuits in close collaboration with physical design engineers to improve cell performance, power and area
collaborating with EDA partners to optimize cell content in standard cell library

Ph.D. or master's degree in electrical engineering or computer science
10+ years of industry experience
Strong technical understanding of advanced semiconductor technology
Strong technical understanding of foundation IP design and design-technology co-optimization
Experience in standard cell library design with good understanding of MOSFET electrical characteristics and local layout effects
Experience with library cell characterization methodology and tools and Spice circuit simulations
Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
Excellent oral and written communication skills
Collaborative mindset and great team player
Good track record of technical leadership and delivery

Principal Engineer, Design Technology Co-optimization

Key skills