Drive innovation and excellence in system-level validation methodologies for advanced integrated SoCs
Define, develop, and execute comprehensive validation methodologies for integrated SoCs
Implement and utilize hardware and software tools to monitor validation coverage
Review design changes to assess impact on validation plans
Develop and maintain validation test plans and post-silicon validation infrastructure
Collaborate with cross-functional teams to optimize SoC interfaces
Perform silicon debug to identify and resolve root causes of functional failures
Publish validation reports summarizing activities and findings
Create and validate content for specific IP interactions
Mentor and develop technical leaders while driving organizational goals through technical vision and strategy

Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field
at least 12 years of relevant experience; alternatively, 8 years of experience with a Master's degree or 6 years with a PhD
Expertise in validation methodologies for SoCs and strong proficiency in hardware debugging techniques
Advanced knowledge of validation tools and techniques, including simulation, emulation, and FPGA environments
Strong technical skills in silicon debug, failure analysis, and performance optimization for complex SoC systems

Senior Principal Engineer, Verification

Key skills