Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
Develop and maintain scripts and automation to improve flow efficiency and consistency.
Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
Assist in chip-level integration, ECOs, and tapeout preparation.
Contribute to methodology development, tool evaluation, and flow documentation.
Support your product through production and spaceflight.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
5–10 years of experience in ASIC physical design for complex SoCs
Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent)
Strong understanding of timing analysis, power optimization, and physical verification flows
Experience with hierarchical or flat SoC design methodologies
Familiarity with FinFET technologies
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation
Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Senior ASIC Physical Design Engineer

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