Execute physical design and layout of ASICs that integrate both analog and digital processing for satellite communication systems
Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs
Develop ASICs that meet the stringent standards of satellite communication, ensuring high performance and efficiency
Perform timing closure, signal integrity analysis, and physical verification (DRC/LVS/ERC)
Implement advanced RF processing technologies that support satellite missions with reduced size, weight, and power (SWaP)
Optimize layouts for radiation tolerance and reliability in the space environment
Collaborate with front-end designers to ensure design intent is preserved through implementation
Perform static timing analysis and address timing violations
Utilize data analytics to optimize ASIC performance and drive innovation in satellite communication
Work with semiconductor foundries to ensure manufacturability and yield optimization
Implement design for test (DFT) structures and methodologies
Document physical design processes, methodologies, and results
Support post-silicon validation and debug activities.

B.S. degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in physical design and layout of ASICs
Demonstrated expertise in digital and analog layout techniques
Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor)
Knowledge of semiconductor fabrication processes and design rules
Understanding of timing closure and signal integrity challenges
Experience with power analysis and optimization techniques
Preferred Qualifications: Experience with mixed-signal or RF layout techniques
Knowledge of radiation-hardened design methodologies
Experience with advanced process nodes (16nm and below)
Background in high-speed digital design (>1GHz)
Experience with 3D packaging or chiplet technologies
Understanding of thermal considerations in ASIC design
Familiarity with space qualification requirements for electronic components
Experience with low-power design techniques for battery or solar-powered systems.

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours
Up to 14 company-paid holidays
Employees may be eligible for benefits and bonuses based on the company's intent

Principal Silicon Physical Design and Layout Engineer

Key skills