Design Verification Engineering Manager

Role Overview

• Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation
• Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications.
• Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
• Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborate Across Teams: Work closely with chiplet architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
• Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
• Lead and mentor others: inspire and guide junior engineers, fostering their growth and development.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
• 6+ years of experience in ASIC/FPGA design verification
• Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and communication protocols (e.g., PCIe, Ethernet, UART, SPI, I2C/I3C))
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.
• Experience with scripting languages.

Benefits

• Health insurance
• Retirement plans
• Stock bonuses
• Vacation