Develop section (multi-hierarchical) level layouts with a focus on quality and efficiency
Collaborate with schematic designers, block layout engineers, and lead layout personnel to meet project milestones
Provide technical guidance, task allocation, and schedule management for block layout resources
Ensure design integrity and compliance with layout principles, reliability, and industry standards
Mentor and train junior engineers and interns, fostering team development
Contribute to layout process enhancements and best practice initiatives

Proven expertise in section-level (multi-hierarchical) IC layout design
Experience in top-level or chip-level layout is an advantage
Strong understanding of semiconductor device physics, cross-sections, and construction
Solid foundation in layout principles, IC reliability, and failure mechanisms
Proficiency with Cadence Virtuoso XL and Calibre verification tools is a strong plus
Bachelor's degree in Electronics or Electrical Engineering
At least 5 years of relevant IC layout design experience
Strong communication skills, both written and oral
Ability to collaborate effectively within a cross-functional, global team
Demonstrated leadership and project coordination capabilities
Layout experience in High Voltage, High-Speed Layouts, Switches, or Multiplexers is a plus
Familiarity with technology nodes such as 0.18µm, 0.35µm, or 40nm is an advantage.

Senior Designer, Layout

Key skills