Drives end-to-end development for substrate design from concept through tapeout and implements physical layout and routing of the package design
Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs
Works closely with silicon and hardware teams to optimize silicon package board performance and pinout
Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design
Completes documentation and collateral into the product lifecycle management system of record

Ph.D. or Master’s in electrical engineering, chemical engineering, mechanical engineering, or material science
10+ years of in-depth knowledge/background in Package, PCB design, or IC digital design
Strong technical background in design and electrical analysis
Solid background in semiconductor fabrication and packaging
Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.
Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx)
Strong analytical ability and problem-solving skills
Ability to work independently and at various levels of abstraction
Strong organization, time management, and communication skills, self-motivated

Packaging Design Architect

Key skills