Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs
Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints
Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams
Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure
Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff
Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up
Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis
Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs
Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts
Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design
Experience working with large, complex SoCs involving multiple IPs and subsystems
Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation
Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation

Principal SoC DFT Engineer, HBM

Key skills