STA Engineer

Role Overview

• DFT STA execution, from rtl driven constraints to STA sign-off
• Be part of a team with deep understanding in all aspects of pre and post silicon
• Work on a variety of challenging designs and unique DFT solutions
• Daily work involves all aspects of static timing analysis
• constraints, environment, models generation and timing ECO generation for block level and full chip level
• Taking part in flows development

Requirements

• B.SC. in Electrical Engineering/Computer Engineering
• 2-3 years of experience as STA engineer
• Ability to quickly adapt to new technology
• Strong communication skills
• Great teammate
• Drive new solutions based on any issues that arise
• Knowledge in physical design flows and methodologies (PNR, STA, physical verification)
• Knowledge in DFT flows such as ATPG, Mbist, Ijtag
• Prior experience in DFT timing closures
• Knowledge in CDC
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)

Benefits

• health insurance
• retirement plans
• paid time off
• flexible work arrangements
• professional development
• bonuses
• stock options