About this role

Develop verification components and API's for cluster and system level test benches
Verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC
Architect the testbenches and craft verification environment using SV, C/C++ methodology
Define test plans, tests and verification infrastructure for clusters and systems
Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
Implement functional coverage and own SOC level verification closure
Work with architects, designers, FPGA, and post-silicon teams to ensure robustness

BTech or MTech in ECE, EE, CSE, or an equivalent degree is required
Over 4 years of experience in verification closure of complex units, sub-systems, or SOC level verification
Proven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch
Experience in the latest verification methodologies like SV and UVM
Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug
Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams

Senior Verification Engineer – HSIO Cluster, SOC

Key skills