About this role

Be responsible for understanding specific protocol concepts and features
Make architectural trade-offs based on feature/performance/power requirements
Analyze system implications, develop micro-architecture
Implement RTL, drive the verification, close timing, and support silicon validation
Own micro-architecture and RTL development of design modules
Micro-architect features to meet performance, power and area requirements
Work with HW architects to define critical features
Collaborate with verification teams to verify correctness

BTech/MTech in EE, ECE or similar stream
3+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
Knowledge of HSIO standards, protocols and architectures of modern SOC's
Excellent influencing skills
Good debugging, analytical and problem solving skills
Working exposure with AI tools like Claude and Cursor would be a plus

Senior ASIC Design Engineer, High Speed IO

Key skills