Develop UVM-based verification test benches and methodologies for unit level
Write verification components and API's for cluster and system level test benches
Verify dedicated CPU sub-systems targeted for Audio processing, Functional Safety, RAS, BOOT and power management
Architect the testbenches and craft verification environment using SV, UVM and C/C++ methodology
Define test plans, tests and verification infrastructure for clusters and systems
Build efficient and reusable bus functional models, monitors, checkers, scoreboards, API's and encapsulated components
Implement functional coverage and own unit, cluster and SOC level verification closure
Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust and feed back and bug escapes driven improvements to your setup

BTech or MTech in ECE, EE, CSE, or an equivalent degree
Over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification
Proven experience in RISCV, ARM or DSP core based CPU sub-systems
Experience in the latest verification methodologies like SV and UVM
Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug
Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization

Senior Verification Engineer – Audio and Auxiliary CPU Sub-Systems

Key skills