About this role
Role Overview
- Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces
- Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards
- Enable ESD protection circuits and latch up safe layout practices across designs and technologies
- Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results
- Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams
Requirements
- Master’s degree or Ph.D. in Electrical Engineering or equivalent industry experience
- Strong fundamentals in ESD physics, latch up mechanisms, and advanced CMOS devices
- Hands-on experience with ESD protection circuits and latch up prevention techniques
- Familiarity with JEDEC and ESDA standards, including HBM, CDM, and JESD78
- Experience supporting ESD and latch up sign-off for advanced DRAM or HBM products
- Knowledge of SCR-based clamps, distributed ESD networks, and rail-based strategies
- Proven ability to mentor engineers and influence design methodology across teams
Benefits
- Health insurance
- Paid time-off program
- Paid family leave
- Income protection programs
- Choice of medical, dental and vision plans