Senior Staff Manager

Role Overview

• Define micro-architecture for complex blocks and subsystems
• Manage a team of 10–12 engineers
• Oversee the entire silicon lifecycle, including RTL design, synthesis, timing closure, and physical design coordination
• Partner with Verification, Physical Design (PD), and DFT (Design for Test) teams
• Align engineering roadmaps with business objectives and manage project budgets

Requirements

• 12–18+ years of hands-on experience in VLSI design
• 3–5 years in a formal management or technical lead capacity
• Expertise in Verilog/SystemVerilog and SoC interconnect protocols like NoC, AXI, and AHB
• Deep understanding of clocking, reset architectures, and CDC/RDC analysis
• Proficiency with EDA tools from vendors like Synopsys or Cadence for synthesis, linting, and static timing analysis
• Bachelor’s or Master’s degree in Electrical or Computer Engineering (specialisation in VLSI preferred)

Benefits

• competitive compensation
• great benefits
• shared collaboration
• transparency
• inclusivity