Responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments
Define verification plans and environment architecture
Develop test cases and test bench components
Coverage analysis and closure, and debug
Work with emulation and FPGA prototyping platforms
Lead efforts in evaluating and driving the adoption of advanced verification methodologies/flows
Develop functional models to facilitate the block, system, and ASIC level verification
Collaborate closely with the design teams and EDA vendors

6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
Experience verifying designs at the block and system levels
Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Experience with Synopsys, Cadence, and Mentor simulations tools
Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
Experience with Perl/Python and Tcl or other scripting languages
Experience with version control systems (DesignSync, git)
Superior writing, grammar, and verbal communication skills
Excellent problem solver; develops and employs automated processes where applicable
Worked independently and in a global team and dynamic environment in a highly visible role
Possesses ability to learn and adapt to new tools and methodologies on the fly
Must have legal authorization to work in the US

Design Verification Engineer

Key skills