Responsible for defining and implementing post-silicon strategies
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows
Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models
Driving re-usable test and debug strategies

Bachelor's or a Master's Degree in Electrical or Computer Engineering required
at least 10 years of experience
Prior experience in post-silicon debug experience from first silicon to production
Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior experience working with Gate level simulation, debugging with VCS and other simulators
Verilog design experience
developing custom DFT logic & IP integration
familiarity with functional verification DFT CAD development
Test Architecture, Methodology and Infrastructure Test
Static Timing Analysis
Post silicon validation using DFT patterns
Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
eligible to earn annual bonuses

ASIC Engineering Technical Leader – DFT

Key skills