Logic Design Engineer

Role Overview

• Write and review micro-architecture specifications
• Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
• Contribute to full chip integration, timing methodology, and analysis
• Collaborate with verification engineers to resolve bugs and achieve coverage closure
• Work with the physical design team to close timing and PnR issues
• Support design methodology evolution and best practices
• Perform debug, root-cause analysis, and post-silicon validation in the lab

Requirements

• B.Sc./M.Sc. in Electrical Engineering from a top university
• 6+ years of experience in a relevant field
• RTL design experience
• Familiarity with UVM and functional verification methodologies
• Experience with MATLAB simulations and bit-exact modeling environments
• Familiarity with mixed-signal systems and environments

Benefits

• Health insurance
• Flexible work arrangements
• Professional development opportunities