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ASIC Design Hardware Engineer – SDC/STA at Cisco | JobVerse
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ASIC Design Hardware Engineer – SDC/STA
Cisco
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ASIC Design Hardware Engineer – SDC/STA
San Jose, California, United States of America
Full Time
57 minutes ago
$152,500 - $219,200 USD
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Key skills
Perl
Shell
About this role
Role Overview
Develop and apply methodology for timing constraints
Collaborate with Front-end and Back-end teams
Contribute to developing next-generation networking chips
Identify and resolve timing issues across all design levels
Work with physical design and DFT teams for full-chip timing closure
Review block level SDCs and clocking diagrams
Guide in refining design and timing constraints for seamless physical design closure
Requirements
Bachelor’s Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience
Master’s Degree in Electrical or Computer Engineering with 2+ years of ASIC or related experience
Experience with synthesis tools (eg. Synopsys DC/DCG/FC)
STA tools such as Primetime
Knowledge of HDL such as Verilog/SystemVerilog programming
Scripting languages such as Shell, Perl
Strong experience scripting with TCL
Experience with digital design concepts (eg. clocking, timing exceptions and async boundaries)
Experience with block/full chip SDC development in functional and test modes
Experience with microarchitecture and RTL implementation
Tech Stack
Perl
Benefits
medical, dental and vision insurance
401(k) plan with matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
optional 10 paid days per full calendar year to volunteer
16 days of paid vacation time for non-exempt employees
flexible vacation time off program for exempt employees (no defined limit)
80 hours of sick time off on hire date and January 1st thereafter
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