About this role
Role Overview
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
- Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
Requirements
- 7 + years of relevant signal and/or power integrity experience
- Proven experience with multiple high-speed ASIC tape-outs from a package perspective.
- Deep expertise in 100G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
- Extensive hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
- Working knowledge of SPICE.
Benefits
- Health insurance
- 401(k) matching
- Flexible work schedule
- Paid time off
- Professional development opportunities