SLD FPGA Verification Engineer III – Lunar Permanence

Role Overview

• Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM)
• Create comprehensive verification and validation plan that encompasses functional and system level verification and validation
• Develop IP/subsystem/system level testbench and tests to achieve required coverage goals
• Document plans and procedures
• Write directed and random test cases
• Generate reports in support of certification of the design to a high DAL.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study
• 5+ years experience verifying FPGAs or ASICSs
• In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent
• In-depth knowledge of System Verilog and the Universal Verification Methodology (UVM)
• Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch
• Experience with predictive testbench components, functional coverage and assertions
• Experience with constrained random verification
• Experience with the Register Abstraction Layer
• Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Bonuses based on the company's intent to reward individual contributions