Contribute to the design, implementation, and validation of advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications
Participate in the definition, design, and verification of high-performance analog blocks and subsystems
Engage in technical discussions and contribute to design reviews
Conduct post-silicon validation and performance optimization
Provide guidance to layout engineers and mentor junior analog designers
Collaborate across disciplines with system architects, digital designers, and layout teams
Develop innovative designs as part of a highly experienced SerDes team focused on next-generation high-speed interconnect solutions

Bachelor’s degree in Electrical Engineering, Electronics Engineering, or in a STEM related field
2+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications
Experience in one or more of the following domains: PLL, CDR, CTLE, DFE, ADC, LDO, Ref Gen, or Transmitter (TX) design
Experience with core analog design principles, including noise, linearity, matching, and stability
Experience with advanced FinFET CMOS process technologies
Experience with analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent
Ph.D. in Electrical Engineering, Electronics Engineering, or in a STEM related field (preferred)
Experience with transmitter and receiver design, CDR loops, and equalization techniques (preferred)
Experience with next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD (preferred)
Experience with high-speed communication standards such as PCIe (Gen4/Gen5) and Ethernet (100G/400G) (preferred)
Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl) (preferred)
Experience with signal integrity concepts, channel modeling, and system-level link analysis (preferred)

Senior Staff Analog Circuit Design Engineer – SerDes

Key skills