Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 7-10 years of experience.
Knowledge of the latest innovative trends in DFT, test and silicon engineering.
Experience with Jtag protocols, Scan insertion and ATPG, Boundary Scan
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
Knowledge of the latest innovative trends in DFT, test and silicon engineering.
Experience working with Gate level simulation, debugging with VCS and other simulators.
Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
Strong verbal skills and ability to thrive in a multifaceted environment
Scripting skills: Tcl, Python/Perl.

ASIC DFT Engineer – 7 to 10 yrs

Key skills