Microarchitecture and design of soft IP cores for Intel’s next generation chips (including SOCs) for different market segments.

Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification
Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) components.
Expertise in verilog and system verilog based logic design.
Experience in Design Quality check tools like linting, synthesis / timing closure, CDC, LEC etc.
Experience in one/more of the following areas PCI_Express, and/or AMBA standards (AXI, AHB etc..)
Knowledge of use of AI tools like Github Copilot.
Knowledge of SVA.
Knowledge of RAS domain is a plus.
Looking for highly motivated individuals and ability to deal with ambiguity.
Knowledge of considerations for performance, power and cost optimization is desirable.
Ability to work in a team environment.

Design Engineer

Key skills