Key skills
PythonC++CAIMentoring
About this role
Role Overview
- Own verification planning and execution for assigned IP blocks and features at IP and subsystem level
- Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure
- Collaborate closely with architecture, design, and software teams
- Analyze simulation failures, root-cause issues quickly, and drive fixes to closure
- Drive functional coverage planning and coverage closure for assigned blocks
- Contribute to both simulation and formal verification efforts
- Begin mentoring junior engineers
Requirements
- BS/MS in Electrical Engineering, Computer Science, or related field
- 8-12 years of relevant experience in design verification
- Strong expertise in interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe
- Strong background in simulation-based verification methodologies including UVM, SVA, and ABV
- Hands-on coding proficiency across System Verilog/UVM, C/C++, and Python
- Comfort using AI-assisted development tools
Tech Stack
- Python
Benefits
- Flexible work arrangements
- Professional development opportunities