Responsible for Defining, leading and owning RTL development of our latest AI-enabled RISC-V CPU core
Drive the micro-architecture and design of critical blocks of the CPU core
Design of RISC-V Vector CPU core and its custom extensions
Design of AI-enabled Matrix engine to augment the Vector CPU
Explore high-performance strategies working with the CPU modeling team
Perform Microarchitecture development and specification
from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications
Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Perform Functional verification support and assist in the design verification strategy
Assist with the verification of RTL design performance goals
Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: * Instruction fetch and decode, branch prediction techniques * Instruction scheduling, register renaming, Reorder Buffer (ROB) * Out-of-order execution * Integer and Floating-point execution * Load/Store execution * Instruction and Data Prefetch * Vector data path * Cache and memory subsystems
Knowledge of Cache coherency and memory consistency
Knowledge of System Verilog, Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications
Master’s with 4-7 years of experience, PhD 2-5 years of work experience

Staff Engineer – AI/ML

Key skills