You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology.
Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems.
Use various front-end simulator tools (VCS/NC) to perform this activity.
Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation.
Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development.
Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology.

Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

ASIC Front-end Verification Engineer

Key skills