Key skills
PerlPythonCommunicationCollaboration
About this role
Role Overview
- lead the MBIST methodology in silicon one chips
- design & implement robust and reusable MBIST architecture
- spec comprehensive MBIST architecture and implementation agnostic to technology and tools
- define MBIST requirements for advanced technology nodes & packages
Requirements
- Bachelors in Electrical engineering plus at least 12+ years (or Master's with 10+ years) experience in ASIC DFT
- prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes
- prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent)
- scripting skills (Python, TCL, Perl) for automation
- ability to plan and execute complex test strategies
- excellent communication skills for cross-team collaboration
- focus on silicon quality and yield improvement
- preferred: experience in Verilog/System Verilog and addressing Memory failure correlation in production
Tech Stack
- Perl
- Python
Benefits
- medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- 10 paid holidays plus 1 floating holiday
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time for non-exempt employees
- flexible vacation time off program for exempt employees
- 80 hours of sick time off
- additional paid time away for family emergencies
- optional 10 paid days per year for volunteering
- eligibility for annual bonuses