Technical Leader

Role Overview

• You will be in the Silicon One development organization as an ASIC Technical Leader
• DFT
• You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
• Involved in crafting groundbreaking next generation networking chips
• Help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases
• Additional exposure to physical design signoff activities
• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams
• Play a key role in full chip design integration with the testability features coordinated in the RTL
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows
• Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die

Requirements

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required
• at least 10 years of experience
• Prior experience working in the latest innovative trends in DFT, test and silicon engineering
• Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators
• Post-silicon validation and debug experience
• Ability to work with ATE patterns, P1687
• Verilog design experience
• developing custom DFT logic & IP integration
• familiarity with functional verification DFT CAD development
• Test Architecture, Methodology and Infrastructure Test
• Static Timing Analysis
• Post silicon validation using DFT patterns

Benefits

• medical, dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• 10 paid holidays per full calendar year
• 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• paid year-end holiday shutdown
• 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year
• Exempt employees participate in Cisco’s flexible vacation time off program
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• Employees are also eligible to earn annual bonuses subject to Cisco’s policies