Ethernet ASIC Design Engineer

Cornelis Networks delivers high-performance scale-out networking solutions for AI and HPC datacenters, and they are seeking a Senior ASIC Design Engineer with extensive experience in Ethernet design. The role involves designing and implementing advanced Ethernet protocols for next-generation switch ASICs, collaborating with verification engineers, and contributing to performance optimization strategies.

Responsibilities:

• Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development
• Develop microarchitecture specifications for Ethernet protocol blocks
• Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues
• Contribute to performance optimization and power-aware design strategies for Ethernet subsystems

Requirements:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
• 10+ years of industry experience in digital design with proficiency in Verilog and System Verilog
• Experience in RTL design for Ethernet protocols relevant to adapters and switches
• Familiarity with timing closure and modern physical design methodologies
• Proven ability in system-level debug and root cause analysis of technical issues
• Strong verbal and written communication skills
• 15+ years of ASIC design experience
• 10+ years of relevant experience in networking hardware design
• Proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec
• Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers)
• Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug
• Expertise in multiple clock domain designs and asynchronous interfaces
• 10+ years of experience with scripting languages such as TCL, Python, or Perl
• Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime