Cornelis Networks delivers high-performance scale-out networking solutions for AI and HPC datacenters. They are seeking a Senior ASIC Verification Engineer responsible for the verification closure of design modules or sub-systems, collaborating with cross-functional teams to ensure the highest design quality.
Responsibilities:
- Participate in ground up development of UVM environments to verify RTL at block, unit, and SoC levels
- Develop and execute functional tests according to verification test plans
- Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
- Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality
Requirements:
- 10 + years of experience with writing code using System Verilog Language
- Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
- Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
- Experience in ground up testbench development
- Experience with revision control systems like Git or SVN etc
- B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
- M. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
- 10 + years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
- One or more scripting languages (TCL, Python, Perl, Shell-scripting)
- Track record of first-pass success in ASIC and Systems