Senior ASIC Design Engineer

Role Overview

• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic
• Collaborate with verification engineers to create block
• and system-level test plans to ensure comprehensive design coverage
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems

Requirements

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
• 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog
• Experience in RTL design for high-speed data paths or packet processing in ASICs
• Deep understanding of Host Ethernet adaptor architectures
• Familiarity with timing closure and modern physical design methodologies
• Proven ability in system-level debug and root cause analysis of technical issues
• Strong verbal and written communication skills

Benefits

• Competitive compensation package that includes equity, cash, and incentives
• Health insurance
• Retirement benefits
• Generous paid holidays
• 401(k) with company match
• Open Time Off (OTO) for regular full-time exempt employees
• Paid time off benefits include sick time, bonding leave, and pregnancy disability leave