Senior FPGA Verification Engineer

Ursa Major is revolutionizing how America and its allies access and apply high-performance propulsion. As a Senior ASIC/FPGA Verification Engineer, you will architect, develop, and execute test benches, verify requirements, and prepare design review materials within the Avionics development team.

Responsibilities:

• Architect and generate ASIC/FPGA test benches
• Generate test cases and run simulations to verify the functionality of ASIC/FPGA code
• Generate and perform testing on target hardware as part of post-silicon validation or integrated test environment (Hardware in the Loop)
• Collect functional and code coverage metrics
• Validate and verify ASIC/FPGA requirements
• Help debug ASIC/FPGA design and/or test issues
• Prepare materials for peer reviews and major program design reviews

Requirements:

• 5+ years' experience with SystemVerilog Universal Verification Methodology (UVM), Pyuvm or similar verification methodology
• Experience with COCOTB and python-based HDL simulations
• Experienced in running ASIC/FPGA simulations using QuestaSim, VCS, Riviero-Pro, or Verilator
• Experienced in collecting ASIC/FPGA coverage metrics
• Experienced in defining test plans, generating test cases and testbench components
• Experienced in writing VHDL, Verilog or SystemVerilog code for ASIC/FPGA design
• Experience in Python scripting, simulations and tool development
• US CITIZENSHIP, PERMANENT RESIDENCY, REFUGEE OR ASYLUM STATUS IS REQUIRED
• Eligibility to obtain and maintain a U.S. Security Clearance
• ASIC/FPGA design experience
• Digital circuit design experience
• Experience with constrained random test benches
• Experienced with assertion-based simulations
• Experience validating DSP-centric designs
• Experience running back-annotated ASIC/FPGA simulations