DFT Design Engineer

Intel is a technology leader seeking a DFT Design Engineer, ideally suited for recent graduates and early-career professionals. In this role, you will design and verify Design for Test (DFT) features for silicon products, ensuring manufacturability and reliability while collaborating with cross-functional teams.

Responsibilities:

• Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP
• Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems
• Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals
• Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation
• Review and execute verification plans to ensure design features meet architecture specifications
• Resolve RTL test failures and implement corrective measures to ensure feature correctness
• Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs
• Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE)
• Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements

Requirements:

• Bachelor's degree in Computer or Electrical Engineering, or a related field with no prior experience required
• Interest in DFT as a career
• This position is based in Fort Collins, Colorado and requires on-site presence 4 days per week at our office location
• Familiarity with test architecture including SCAN, MBIST, BSCAN, and TAP
• Familiarity with RTL coding, DFT techniques, and timing closure methods
• Experience with design tools and methodologies such as ATPG and coverage analysis
• Experience configuring EDT setups and resolving stuck-at and at-speed test scenarios
• Proficient programming skills in TCL, Python, Perl, and/or C++
• Knowledge of GLS for test scenario resolution and ATPG coverage analysis
• Strong communication and collaboration skills, with a focus on teamwork across diverse engineering groups