Cornelis NetworksRemote
Ethernet ASIC Design Engineer
United States of America
Full Time
3 weeks ago
No H1B
Key skills
ASIC DesignEthernet ProtocolsVerilogSystem VerilogRTL DesignTiming ClosurePhysical Design MethodologiesSystem-level DebugRoot Cause AnalysisEthernet MACL2/L3/L4 Networking ProtocolsMultiple Clock Domain DesignAsynchronous InterfacesScripting Languages - TCLScripting Languages - PythonScripting Languages - PerlEDA Tools - Design CompilerEDA Tools - SpyglassEDA Tools - PrimeTimePythonPerlAIPerformance OptimizationCommunication
About this role
Cornelis Networks delivers high performance scale-out networking solutions for AI and HPC datacenters. They are seeking Ethernet ASIC Design Engineers with deep experience in ASIC design, particularly in networking hardware and Ethernet protocols, to contribute to the development of next-generation Ethernet switch ASICs.
Responsibilities:
- Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development
- Develop microarchitecture specifications for Ethernet protocol blocks
- Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog
- Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage
- Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
- Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues
- Contribute to performance optimization and power-aware design strategies for Ethernet subsystems
Requirements:
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
- 10+ years of industry experience in digital design with proficiency in Verilog and System Verilog
- Experience in RTL design for Ethernet protocols relevant to adapters and switches
- Familiarity with timing closure and modern physical design methodologies
- Proven ability in system-level debug and root cause analysis of technical issues
- Strong verbal and written communication skills
- 15+ years of ASIC design experience
- 10+ years of relevant experience in networking hardware design
- Proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec
- Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers)
- Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug
- Expertise in multiple clock domain designs and asynchronous interfaces
- 10+ years of experience with scripting languages such as TCL, Python, or Perl
- Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime