Senior Radar FPGA/Embedded Systems Engineer

LeoLabs is building the living map of activity in space through their global radar network and AI-enabled analytics platform. They are seeking a Senior Radar FPGA/Embedded Systems Engineer to support their Radar Systems group by developing and maintaining advanced software for phased array radars, directly impacting mission-critical radar systems for national security and commercial space operations.

Responsibilities:

• Own and maintain the Xilinx Vivado + Yocto project(s) end-to-end
• Modernize and harden the development and production environments
• Update the existing projects to build and run on current Xilinx tool versions
• Establish a reliable process to build, package, and deploy FPGA/boot images to devices (local and remote)
• Significantly improve the FPGA verification and regression infrastructure
• Add observability and diagnostics for on-target debug (ILA/VIO, counters, assertions/health monitors) and define acceptance tests for new releases
• Be comfortable reading and writing C and Rust for embedded targets to support FPGA integration
• Define and maintain clean FPGA software contracts to support long-term maintainability

Requirements:

• Must be eligible to obtain and maintain a U.S. personnel security clearance
• Bachelor's degree in EE/CE (or related) plus 8+ years of relevant FPGA experience (or equivalent advanced degree + fewer years)
• Excellent communications skills, must be able to communicate highly technical ideas in a manner that is comprehensible to a team composed of individuals from diverse disciplines
• Strong, demonstrated experience owning production Xilinx FPGA projects (Vivado, constraints, IP integration), plus embedded Linux exposure
• Direct experience with Xilinx RFSoC devices (architecture, data converters, clocking, tool flow, common pitfalls)
• Ability to take an HDL module through the full FPGA flow on an SoC platform
• Experience operating and updating Yocto/AMD EDF-based systems in the field, including remote update/deployment workflows
• Experience writing performant C (and/or Rust) code for embedded systems, and optimizing for highly constrained environments
• Practical experience with coherent timing systems (10 MHz / 1PPS) and debugging timing-sensitive field issues
• Modify and improve FPGA-based RF/radar signal processing chains
• Work with RF/signal-processing stakeholders to translate performance needs into FPGA changes
• Manage fixed-point design tradeoffs and validate against system-level metrics