B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Design Verification Engineer

Key skills