ASIC Packaging Signal Integrity Hardware Engineering Technical Lead (Remote)

Cisco is a leading company in building complex and high-performance Silicon ASICs. They are seeking a Signal and Power Integrity Technical Lead to develop next-generation ASIC packaging, ensuring power, performance, and area goals are met while collaborating across teams to resolve technical issues.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams

Requirements:

• Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and/or power integrity experience
• Proven experience with multiple high-speed ASIC tape-outs from a package perspective
• Deep expertise in 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters
• Extensive hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review
• Working knowledge of SPICE
• Prior experience leading small to medium technical teams
• Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing
• Experience with advanced nodes (5nm, 3nm and below)
• Background in high-bandwidth memory (HBM) or high-speed memory interface SI
• Experience with die-to-die interfaces (UCIe or proprietary)
• Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging
• Experience with MATLAB or Python scripting
• Experience with Raptor-X
• Working knowledge of Vector Network Analysis
• Basic knowledge of IBIS