Key skills
PythonC++CPerlShellAIMLGitSVNMercurialAgile
About this role
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.
As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
* Develop functional tests based on verification test plan
* Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
* Debug, root-cause and resolve functional failures in the design, partnering with the Design team
* Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
* Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
* 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
* 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
* Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience working across and building relationships with cross-functional design, model and emulation teams
* Experience with revision control systems like Mercurial(Hg), Git or SVN
* Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
* Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
* Track record of 'first-pass success' in ASIC development cycles
* Experience with micro-architectural performance verification
* Experience verifying GPU/CPU designs
* Experience with verification of ARM/RISC-V based sub-systems or SoCs
* Experience in development of UVM based verification environments from scratch
* Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet
* Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
* Develop functional tests based on verification test plan
* Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
* Debug, root-cause and resolve functional failures in the design, partnering with the Design team
* Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
* Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
* 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
* 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
* Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience working across and building relationships with cross-functional design, model and emulation teams
* Experience with revision control systems like Mercurial(Hg), Git or SVN
* Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
* Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
* Track record of 'first-pass success' in ASIC development cycles
* Experience with micro-architectural performance verification
* Experience verifying GPU/CPU designs
* Experience with verification of ARM/RISC-V based sub-systems or SoCs
* Experience in development of UVM based verification environments from scratch
* Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet
* Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation