Job Title: Senior HW Design Test Engineer
Location: Santa Clara, CA (Onsite)
Experience: 12 15 years
Key Responsibilities:
Establish long-term test strategies covering NPI, sustaining, and manufacturing.
Identify systemic quality risks early and drive mitigation plans before release.
Hardware & System Expertise
Deeply understand and review schematics, board layouts, and system architecture.
Anticipate and debug complex issues involving:
Power sequencing, reset topology, clocks
High-speed interfaces (PCIe, Ethernet, SerDes)
Memory subsystems (DDR, HBM, flash)
Drive root-cause analysis across ASIC, hardware, firmware, and OS boundaries.
Cross-Functional Leadership
Partner with Hardware, ASIC, Platform, Software, and Manufacturing teams to influence design-for-test and reliability.
Represent test engineering in architecture reviews, EC/ECO discussions, and readiness reviews.
Mentor senior engineers and raise the overall technical bar of the test organization.
Manufacturing & Production Impact
Guide manufacturing test strategy, yield improvement, and failure triage at CM sites.
Prevent unnecessary hardware scrap through strong root-cause analysis and software mitigation.
Drive alignment between lab validation and factory test coverage.
Qualifications:
Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
10 15+ years of experience in test, validation, systems, or hardware/software integration roles.
Deep expertise in hardware circuitry and system architecture
