ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)

Cisco develops hardware platforms, silicon, optics, and ASIC solutions for switching, routing, wireless, and data center products. The company is seeking an ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead to define, design, and verify next-generation ASIC packaging, while leading signal and power integrity analysis, collaborating across engineering teams, and mentoring engineers.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams

Requirements:

• • Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 4+ years of relevant signal and power integrity experience
• • High-Speed Design & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
• • SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
• • Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation
• • Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation
• • Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing
• • Experience with high-bandwidth memory (HBM) or high-speed memory interface SI
• • Experience with die-to-die interfaces (UCIe or proprietary)
• • Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging
• • Working knowledge of Vector Network Analysis
• • Basic knowledge of IBIS