DESIGN VERIFICATION ENGINEER

ROLE: DESIGN VERIFICATION ENGINEER

INTERVIEW: 2 ROUNDS OF WEBCAM

 THIS IS CORP 2 CORP (SUNNYVALE,CA) -CITIZEN/H1BEAD -Locals Preferred

 OVERALL EXPERIENCE 10YRS+

 Rate Max:$80/Hr On C2C

 Job Description:

We are seeking a talented and experienced Design Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in universal verification methodologies and hands-on experience in verifying complex digital designs.

Responsibilities:

·         Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

·         Develop functional tests based on verification test plan

·         Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

·         Debug, root-cause, and resolve functional failures in the design, partnering with the Design team

·         Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality

·         Develop and execute comprehensive verification plans to ensure design quality and functionality.

·         Implement coverage-driven verification strategies to achieve thorough testing of design features.

·         Utilize SystemVerilog (SV) and Universal Verification Methodology (UVM) for creating and executing testbenches.

·         Perform debugging and root-cause analysis to identify issues and ensure timely resolution.

·         Drive design verification closure by ensuring all identified issues are addressed and resolved effectively.

Minimum Qualifications:

·         B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science

·         10+ years of proven experience as a Design Verification Engineer.

·         Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology

·         Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies

·         Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.

·         Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications:

·         Experience in the development of UVM based verification environments from scratch

·         Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs

·         Experience with revision control systems like Mercurial(Hg), Git or SVN

·         Experience with verification of ARM/RISC-V based sub-systems or SoCs