About this role

Work alongside experienced design and verification engineers to help design, verify, and validate FPGA-based solutions.
Provides hands-on exposure to real engineering challenges, modern verification methodologies, and industry-standard tools.

Currently enrolled in a BS or MS degree program in Electrical Engineering or Computer Engineering.
BS students must be at Junior or Senior standing with a minimum GPA of 3.2.
MS students must also maintain a minimum GPA of 3.2.
Coursework must include: FPGA design using Verilog, SystemVerilog, or another HDL.
FPGA verification using Verilog, SystemVerilog, or another HDL.
Excellent written and verbal communication skills.
Ability to thrive in a fast-paced engineering environment.
Strong self-starter mindset with the ability to identify gaps in knowledge and proactively seek answers.
Must be available to work on-site at the North Reading, Massachusetts office.
Must be available to work during the summer break (May–September 2026), based on school schedule.

Logic Design Intern, FPGA Design Verification

Key skills