Set and refine a multi-generational roadmap for HSIO and D2D IP development
Engage directly with senior Intel architects and executives to define IP landing zones
Drive IP development across architecture, logic, validation and analog design teams
Manage competing requirements, schedules, and resource balancing across multiple functional teams
Ensure high quality and on-time IP delivery, including proactive risk management
Lead and develop a high-performing global team of engineers
Foster a culture where issues surface and are addressed early
Drive efficiency throughout the development cycle, including the adoption of AI solutions

Bachelor's degree in Electrical Engineering, Computer Science, or a related field
12+ years of experience
Proven deep experience in analog IP development
10+ years of proven success building, leading, and driving execution in silicon teams delivering complex programs
10+ years of experience leading analog IP design teams
Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe
Demonstrated success managing global, multi-disciplinary engineering organizations
Experience navigating complex SOC customer negotiations

Senior Director, IO Analog Design Engineering

Key skills