About this role
Role Overview
- Functional verification on custom mixed-signal ASICs
- Developing detailed verification plans, methodology, and test-bench infrastructure
- Developing constraint-random and directed tests, scoreboards, and checks
- Coverage implementation, analysis, and closure
- Perform regression triage, failure analysis, and resolution
- Run gate-level simulations, analyze and resolve fails and timing violations
- Work closely with digital/analog designers, systems, applications, and manufacturing test engineers
Requirements
- Bachelor’s degree in Electrical or Computer Engineering and 7+ years of experience working on block-level or chip-level design verification for ASICs.
- Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera)
Benefits
- inclusive and fair culture
- meaningful community engagement
- enjoyable employee experiences