We will incorporate you on a team that is involved in all aspects of physical implementation from RTL to GDSII.
Perform RTL synthesis and scan stitching.
Apply deep knowledge of timing optimization and experience with ECO generation to analyze and fix timing issues in 40nm, 28nm and below.
You will be defining and debugging Timing Constraints and performing STA using industry-standard STA engines and a deep understanding of timing correlation to achieve timing closure.
Build timing constraints for the entire chip in a team environment.
Knowledge of automating and advancing flows using proficiency in Perl/Tcl scripting.
Analyze power constraints and chip floor plan.
You will analyze clock distribution on full-chip assembly.
Physical design-related flow development, tool evaluation, flow automation, QA and improvement.
You will develop Placement & Route structures for a complete ASIC design.
Build Static Timing Analysis, timing closure, ECO and tape-out.
IR Drop analysis and improvement on almost all designs

Bachelor's or Master's in Electrical Engineering and 5+ years of industry experience in a Logic design or Physical Design position.
Strong solid understanding of RTL design, and the ideal candidate should be familiar with Cadence Genus/Innovus and Synopsys Design Compiler/ICC/Fusion Compiler
You should have Primetime, Conformal LEC, and ATPG.
You will also have a solid understanding of scan insertion, and ATPG.
Good communication and collaboration skills.

Cirrus Logic strives to select the best qualified applicant for any opening.
Different approaches, ideas and points of view are both valued and respected.
Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

Physical Design Engineer

Key skills