Performs physical design implementation of custom IP and SoC designs from RTL to GDS
Conducts all aspects of the physical design flow including synthesis, place and route, and static timing analysis
Conducts verification and signoff including formal equivalence verification and static timing analysis
Analyzes results and makes recommendations to fix violations
Optimizes design to improve power, frequency, and area
Participates in the development and improvement of physical design methodologies and flow automation

Bachelor's degree in electrical or computer engineering, or a related field
1 year experience with CMOS transistor level circuit fundamentals or VLSI hardware design
6 months experience with APR tools, either Synopsys Fusion Compiler or Cadence Innovus
6 months experience with Static Timing Analysis (STA)
6 months experience with TCL, Python, or Perl programming

Physical Design Engineer

Key skills