Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog
Translate algorithmic and architectural specifications into synthesizable RTL
Implement DSP functions such as filtering, FFT/IFFT, or beamforming
Convert chip specifications into RTL using internal IPs and external IPs
Design and develop RTL for interfaces, power management, clocking, reset, test & debug
Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic
Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration
Contribute to block-level integration, synthesis, and timing closure
Participate in design reviews, functional verification, and timing closure
Participate in chip bring-up and lab validation of complex digital subsystems
Support your product through production and spaceflight

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on experience in digital ASIC design
Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools
Experience in micro-architecture definition from architecture guideline and model analysis
Experience with DFT tools for scan and BIST insertion
Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification
Familiarity with EDA tools for design, simulation, linting, and STA
Experience implementing DSP functions in hardware
Understanding of digital design best practices including clock domain crossing (CDC), power domain management, and design-for-test (DFT)
Strong debugging, problem-solving, and communication skills

Senior Digital ASIC Design Engineer

Key skills