Design and develop high-performance, high-speed ADC and DAC architectures.
Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems.
Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
Perform design optimization for power, area, and performance in advanced FinFET nodes.
Develop and maintain design documentation and support post-silicon bring-up and characterization.
Support your product through production and spaceflight.
Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

M.S. or Ph.D. in Electrical Engineering with a strong focus in analog/mixed-signal IC design.
5+ years of relevant industry experience in mixed-signal circuit design.
Proven hands-on experience in high-speed ADC/DAC designs with deep understanding of architectures, performance metrics, and design trade-offs.
Strong knowledge of PLL design principles, including charge pump, VCO, loop filter, multi-modulus divider, sigma delta modulator, and jitter analysis.
Solid understanding of FinFET CMOS process characteristics and layout parasitic considerations.
Proficient in EDA tools such as Cadence Virtuoso, Spectre, behavioral modeling (Verilog-A, Verilog-AMS, MATLAB), and similar tools.
Strong debugging, problem-solving, and communication skills.

Senior Mixed-Signal IC Design Engineer

Key skills